Tag Cell
Transistor Layout

VLSI Layout
Information:
The tag cell will be used by the tag memory portion of our CAM. Notice that it is dual ported. It is far more complex then the data cell because it requires the addition of a match line.

Specs:
Speed: Negligable
Size: 120 x 60

# transisters: 3808
# drawn trans: 15
replication factor: 256x
active area vs. routing area: 184512 / 1736448 = 0.63%
total area/block: 1736448 lambda sq.
area vs # trans: 456 lambda sq / tran.
power consumption: 44.4 E -12 W
design time: 40 hrs.

Modifications:
  • Transistor sizing for PMOS and NMOS transistors now uniform, verses the 3-1 ratio. Size of cell reduced by 35%. (Old Layout)
  • Match Line circuitry was simplified.

    Downloads:
    Tag Cell Layout