Sense Amp:
Information:
The sense amp will only be used on the read operation. It's job will be to detect a minute swing in voltage on the bit lines during a read operation, and translate it to a solid 1 or 0.

We were experiencing some heavy problems testing sense amp with the data/tag cells. Apparently, the components tested out ok when simulated individually. However, when connected together, the components failed to simulate properly. Extensive debugging was enacted with no prevail.

In the end, it turns out that our components do in fact work together. So why were we getting incorrect results? I am not positive, but I blame a possible over site of the test sequence of the components.

Click here for a Cazm simulation showing a proper simulation of "write 1, read 1, write 0, read 0." repeated many times. (Note: in this simulation the sense amp was connected to a write buffer, precharge unit and one data cell. [gif image])

Click here for a more specific simulation of the unit.


Specs:
Speed: < 4ns
Size: 114 x 60 lamba

# transistors: 160
# drawn trans: 10
replication factor: 16x
active area vs. routing area: 2016/4824 = 41.8%
total area/block: 6840 lambda sq.
area vs # trans: 42.75 lambda sq / tran.
power consumption: 7.5 E -12 W
design time: 80 hrs.

Modification:

"Sense enable" signals routed with polysilicon. Size reduced from 136 x 107 lambda.

Original "dual sense-amp" design abandoned. A single sense amps will used for both pairs of bitlines instead.

Downloads:
Senseamp Layout