Decoder:


VLSI Layout


IRSIM Simulation


Cazm Simulation of priotity encoder

Information:
Translates a 5-bit binary value into a "one hot" 32-bit value.
Specs:
Speed: 15ns
Size: 480 x 1330 lambda

# transistors: 372
# drawn trans: 12
replication factor: 31x
active area vs. routing area: 32484/307228 = 10.57%
total area/block: 339712 lambda sq.
area vs # trans: 913.2 lambda sq / tran.
power consumption: 18.71 E -12 W
design time: n/a

Modifications:
Positioning of cells changed to simplify routing. Size of cell reduced. (Old Layout.)


Downloads:
Decoder Layout