Data Cell:
Transister Layout

VLSI Layout

Information:
The data cell will be used by the data memory portion of our CAM. Notice that it is dual ported.

Specs:
Speed: Negligable
Size 78 x 60

# transisters: 2048
# drawn trans: 4
replication factor: 256x
active area vs. routing area: 86016 / 875520= 9.83%
total area/block: 875520 lambda sq.
area vs # trans: 427.5 lambda sq / tran.
power consumption: 12.8 E -12 W
design time: 36 hrs.

Modifications:
  • Transistor sizing for PMOS and NMOS transistors now uniform, verses the 3-1 ratio. Size of cell reduced by 35%. (Old Layout.)

    Downloads:
    DataCell Layout