C2MOS Latch:
Transistor Layout
VLSI Layout of registor 5- C2MOS Latches arrayed to form a 5-bit registor.

Information:
This device will be at the heart of the registers used in the circuit. The registers themselfs will be used to latch on to value inbetween the rising and falling edge of the clock so we can reutilize some aspects of the hardware within the same clock.

Specs:
Speed: Negligable
Size: 127 x 276 lambda

Modifications:
None.

Downloads:
Registers (5) Layout