Problem: How many widgets can we reliably connect to the I2C bus via the HUB while having a decent max bus length and a respectable data transfer rate? Requirements: It was agreed upon in class that a long network cable length and a respectable cap on the number of widgets to a network was preferred over a fast data transfer rate. (No one in the class could justify a legitimate need to transfer the entire content of the PIC chip a few times per second!) The following list summarizes the constraints on the design of the network. Numerical values from the previous analysis are used to give a perspective on what values to shoot for: 1) Maximum Network Length (in feet): > 50 ft 2) Maximum Number of Widget / Network: ~ 25 widgets 3) Maximum Data / Clock Rate: << 100 Kbps* * A reduction of 50% or more is acceptable. Assumptions: Let’s first define what we know about the network and assign names to the unknown quantities.
Notes: 1) _{} 2) We will be using CAT5 cabling to connect widgets together. According to many websites I have visited, the capacitance per foot for this grade of cabling is 17 pF or less. I have selected 18 pF to be a little conservative. The resistance per foot is 28.6 ohms/1000 ft or 0.286 ohms/ft
Analysis: What we want to do is first solve for the time constant _{}(or RC) in terms of the 3 constraints. With this value, we can then unify out model with the I2C specification to yield numbers for our three constraints. Calculating
_{}: To calculate this value, we need to model the network. There are two cases which we need to look at: a) the PIC pulls the bus low b) the PIC releases control of the bus and the pullup resister pulls the bus high Lets first look at total capacitance. Obviously, there are not capacitors connected directly to the bus. However, the capacitance of the cabling, the solder joints in the widget, the connectors, etc, creates parasitic capacitance onto the network. These parasitic capacitors are modeled as a capacitor connected to ground off the bus. Since these capacitors are in parallel, the total capacitance is equation to the sum of the capacitance of the network plus that of the widgets, or _{}.
Whenever a PIC goes to pull the bus low, it is drawing current from the voltage supply of the hub, across its pullup resistor, across the network and then into the PIC. Thus, the resistance it sees is _{}or the resistance of the pullup resistor and that of the network wiring. One could argue that is the hub was located in the middle of the network, then the resistance would be lower. This is true, but not 100% accurate. Whenever a PIC releases control of the bus, the pullup resistors will pull it high. In the process of pulling it high, the parasitic capacitors on the bus will be absorbing some of the charge generated by the voltage supply of the hub until they reach a steady state. As a result, the bus will take time to reach the desired 5 Volts. Furthermore, ALL the parasitic capacitors connected to the bus will have an effect because they are in essence connected to ground. Since there is resistance on the bus between the source and each capacitor, we cannot simplify the model by a cleaver placement of the hub.
A module of the network is shown in Figure 2 below.
Thus, the value of _{}is merely _{} Unifying _{}to the Spec: The value of _{}tells us the rise time of the signal to transition from 0% of the voltage to 63% of the voltage. (And likewise in reverse for fall time.) The I2C specification states that the duration of the rise time and fall time for a 100Kbps cock must be no greater than 300nS. It classifies the rise time in terms of the voltage transition from 10% of the voltage to 90%. (And likewise in reverse for the fall time.) (Refer to Figure 3 below.)
The challenge now is to equate the value of _{}with the maximum rise/fall time given by the specification for a 100Khz clock. (It shall be stated explicitly that the analysis will assume that a division of n in the clock frequency will extend the rise/fall time by n. In order words, if the clock was reduced to 50 KHz, then the max rise/fall time is doubled to 600nS.) The equation to express the transient behavior of a capacitor in an RC circuit is _{.} _{For simplicity, let V = 1. We want to find values for R and C where the signal reaches 10% and then 90% of its output voltage, or 0.1 and 09., respectively. This expression can be written as:} _{} We want to solve for RC so we can define the constraints of the system. The first step is to free the _{}, so take the ln of both sides, _{}, which yields _{}. Solving for _{}yields: _{}. Separating the two sets of values yields two separate equations: _{} _{}. In terms of fall time, we want the difference in voltage from 90% to 10% to take 300nS or less, or _{.} (The reverse is true for rise time. Since they are the same, we will stick with calculating the values in terms of the case of the fall time.) Substituting in for the_{}’s yields: _{} Thus, the value of RC for a 100KHz clock must be less than _{} _{}_{,} where _{}. For convention, we will define the quantity _{} This equation is in terms of the max cable length and the max number of widgets. It does not account for the max clock rate directly. Usage of this third constraint is shown in the next section. _{}is set to 231 ohms to set it to its maximum value due manufacturing tolerances. (220 * 1.05 = 231) Obtaining
Values for the Constraints: To determine the values of the constraints, a table in EXCEL was generated and numbers were pluggedin to comeup with values for these constraints. A “slack margin” is considered because the model may have left out some details. To compensate, a buffer from the lower limit is considered. It was recommended that a “slack margin” of 30% to 50% be considered.
Below are the results from the study:
From Figure 4, we can tell that if we want to run the network reliably at a clock rate of 100KHz, then we can have at most 18 feet of cabling with 6 connected widgets. It is highly recommended that the clock rate be set to 25Khz so we can have a max cable length of 75 ft with a 25 widget cap.
