CMPSCI 635 - Modern Computer Architecture

CMPSCI 635 - Course Project

A common trend in microprocessor designs today is to increase the depth of its pipelines. Doing so can better exploit the available parallelism in code, which results in an increase in performance.

However, as the pipeline grows in length, so does the miss penalty. The solution to rising miss penalties has been installing more accurate branch predictors. However, the more accurate the branch predictor, the more chip area (silicon) is required.

The purpose of this paper is to see if there is a trend between various branch predictors, their table sizes (number of entries), and the applications that are commonly run on them to help more efficiently use available silicon area.

The paper explores the behavior of a g-share, bi-modal (BTB) and tournament predictor while running on ten of the SPEC200 test benches. The table sizes are varied to see if any interesting patterns emerge among the branch predictors.

  • Download "Effects of Various Branch Predictors with Varying Table Sizes on SPEC2000 Test Benches" (06/02/04)


  • Snap-shot of how much processing power one simulation ate.
  • A message someone sent to me in regards to my excessive procesing power consumption.

    Contact - wacko at emulationzone d0t org
    Last updated: 01-14-06
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